Equivalent Circuit Models for Strained Si NMOSFET Using Verilog-A

Abstract

Equivalent circuit models for strained Si NMOSFET at DC and AC working conditions are investigated in this article. The intrinsic region, source/drain parasitic regions, and substrate parasitic resistance are proposed respectively. The model admits analytical solution using the quasi-two-dimensional analysis and coherent smoothing functions, a unified drain current model is presented. We also present a unified charge model with the charge as the state variable. Model parameters are extracted from the experimental results by software. Furthermore, simulations for strained Si NMOSFETs are realized using Verilog-A.