A CMOS Pulse-Shrinking Mechanism with Improved Resolution

Abstract

A new CMOS time measurement mechanism based on pulse shrinking applicable to time-to-digital converters (TDCs) is presented to improve resolution. In previous mechanism, the resolution was determined by controlling size ratio between an inhomogeneous and homogeneous logic gates to achieve sub-gate resolution. By only adding an inhomogeneous gate with identical size on the previous mechanism, the proposed mechanism possesses not only a resolution improvement but also a better resolution fluctuation for process and temperature variations. The proposed work was implemented in a 0.35-μm CMOS process for performance evaluation. The results demonstrated that the proposed mechanism achieves a significant resolution improvement with better resolution insensitivity to the process and temperature variations.