A Discuss on a Thermal Conductive Panel of FPGA
Abstract
In this paper a mounted problem about a thermal conductive panel which is used for a FPGA chip being used on satellite and in vacuum environment is discussed. In order to decide whether the panel could be un-mounted when carrying electronic testing in air condition under high and low temperature environment, a simulation analysis is done and the different of convection for the air condition and the thermal contact resistance is considered. The analysis results showed that the temperature of FPGA un-mounting the thermal conductive panel is within the permitted temperature and the final testing have been done in which the box work well. Through the efficiency analysis the time cost and project cost are all saved.
Keywords
Thermal analysis, CAE, Finite element analysis, Contact thermal resistance
DOI
10.12783/dtetr/mcae2017/15938
10.12783/dtetr/mcae2017/15938
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