Design of NAND/NOR Logic Gate Clocked by Voltage-generated Stress

Abstract

By using the preferred magnetization of clock-tilted nanomagnet, we propose a design of NAND/NOR magnetic logic gates clocked by voltage-generated stress. Unlike designs based on slanted nanomagnet, our design uses regular-shaped nanomagnets, allowing high ratio (2:1) of the nanomagnets to be used. It can eliminate C-shaped and eddy current clock errors, and reduce the complexities of fabrication process. In addition, our design consumes only one-tenth the energy of general designs using a spintronics clock.